wolfIP NXP QorIQ FMan port (also big endian fix for ee16/ee32)

src/port/common/nxp_mem.h

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+/* nxp_mem.h
+ *
+ * Freestanding byte-loop memcpy/memset shared by the NXP wolfIP ethernet
+ * ports (the drivers run bare-metal with no libc).
+ *
+ * Copyright (C) 2026 wolfSSL Inc.
+ *
+ * This file is part of wolfIP TCP/IP stack.
+ *
+ * wolfIP is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfIP is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+#ifndef WOLFIP_NXP_MEM_H
+#define WOLFIP_NXP_MEM_H
+
+#include <stdint.h>
+
+static void *nxp_memcpy(void *dst, const void *src, uint32_t n)
+{
+    uint8_t *d = (uint8_t *)dst;
+    const uint8_t *s = (const uint8_t *)src;
+    while (n--)
+        *d++ = *s++;
+    return dst;
+}
+
+static void nxp_memset(void *dst, int c, uint32_t n)
+{
+    uint8_t *d = (uint8_t *)dst;
+    while (n--)
+        *d++ = (uint8_t)c;
+}
+
+#endif /* WOLFIP_NXP_MEM_H */

src/port/common/nxp_phy.h

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+/* nxp_phy.h
+ *
+ * Shared clause-22 PHY register map and bring-up (reset + auto-negotiation +
+ * address discovery) for the NXP wolfIP ethernet ports. The logic is identical
+ * across the ports; only the MDIO-controller accessor differs, so the including
+ * port defines NXP_MDIO_READ(phy,reg) -> uint16_t and NXP_MDIO_WRITE(phy,reg,
+ * val) -> int (0 on success) before including this header, e.g.:
+ *     #define NXP_MDIO_READ  phy_read
+ *     #define NXP_MDIO_WRITE phy_write
+ *     #include "../common/nxp_phy.h"
+ *
+ * Copyright (C) 2026 wolfSSL Inc.
+ *
+ * This file is part of wolfIP TCP/IP stack.
+ *
+ * wolfIP is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfIP is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+#ifndef WOLFIP_NXP_PHY_H
+#define WOLFIP_NXP_PHY_H
+
+#include <stdint.h>
+
+/* Clause-22 PHY register map + bits (IEEE 802.3). */
+#define PHY_BMCR        0x00U
+#define PHY_BMSR        0x01U
+#define PHY_ID1         0x02U
+#define PHY_ID2         0x03U
+#define PHY_ANAR        0x04U
+
+#define BMCR_RESET          (1U << 15)
+#define BMCR_AUTONEG_EN     (1U << 12)
+#define BMCR_POWER_DOWN     (1U << 11)
+#define BMCR_ISOLATE        (1U << 10)
+#define BMCR_RESTART_ANEG   (1U << 9)
+#define BMSR_LINK           (1U << 2)
+#define BMSR_ANEG_COMPLETE  (1U << 5)
+#define ANAR_DEFAULT        0x01E1U
+#define MDIO_TIMEOUT        1000000U
+
+/* The reset/autoneg helpers are provided only when the including port defines
+ * NXP_PHY_HELPERS (i.e. it has an MDIO write path). A fixed-link port includes
+ * this header for the register defines alone. */
+#ifdef NXP_PHY_HELPERS
+#if !defined(NXP_MDIO_READ) || !defined(NXP_MDIO_WRITE)
+#error "define NXP_MDIO_READ and NXP_MDIO_WRITE before including nxp_phy.h"
+#endif
+
+/* Probe the configured PHY address, else scan 0..31. Returns the PHY MDIO
+ * address, or -1 if none responds. */
+static inline int32_t nxp_phy_detect(uint32_t cfg_addr)
+{
+    uint32_t addr;
+    uint16_t id;
+
+    id = NXP_MDIO_READ(cfg_addr, PHY_ID1);
+    if (id != 0xFFFFU && id != 0x0000U)
+        return (int32_t)cfg_addr;
+    for (addr = 0; addr < 32U; addr++) {
+        id = NXP_MDIO_READ(addr, PHY_ID1);
+        if (id != 0xFFFFU && id != 0x0000U)
+            return (int32_t)addr;
+    }
+    return -1;
+}
+
+/* Reset the PHY and restart auto-negotiation. Returns 0 on success, <0 on a
+ * hard failure (reset never cleared or an MDIO write failed), or 1 if
+ * auto-negotiation did not complete in time (a soft condition, e.g. no cable --
+ * the caller can still bring the datapath up and read the live link state). */
+static inline int nxp_phy_init(uint32_t phy)
+{
+    uint32_t timeout;
+    uint16_t ctrl, bsr;
+
+    if (NXP_MDIO_WRITE(phy, PHY_BMCR, BMCR_RESET) != 0)
+        return -1;
+    timeout = MDIO_TIMEOUT;
+    do {
+        ctrl = NXP_MDIO_READ(phy, PHY_BMCR);
+    } while ((ctrl & BMCR_RESET) && --timeout);
+    if (timeout == 0)
+        return -1; /* reset never cleared: PHY absent/stuck */
+
+    if (NXP_MDIO_WRITE(phy, PHY_ANAR, ANAR_DEFAULT) != 0)
+        return -1;
+
+    ctrl &= ~(BMCR_POWER_DOWN | BMCR_ISOLATE);
+    ctrl |= BMCR_AUTONEG_EN | BMCR_RESTART_ANEG;
+    if (NXP_MDIO_WRITE(phy, PHY_BMCR, ctrl) != 0)
+        return -1;
+
+    timeout = MDIO_TIMEOUT;
+    do {
+        bsr = NXP_MDIO_READ(phy, PHY_BMSR);
+    } while (!(bsr & BMSR_ANEG_COMPLETE) && --timeout);
+    if (timeout == 0)
+        return 1;
+    return 0;
+}
+#endif /* NXP_PHY_HELPERS */
+
+#endif /* WOLFIP_NXP_PHY_H */

src/port/nxp_enetc/README.md

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+# wolfIP NXP ENETC port
+
+Ethernet driver for the NXP ENETC integrated-endpoint MAC found on Layerscape parts (lead target: LS1028A, Cortex-A72, AArch64, little-endian). ENETC appears as PCI functions on an internal ECAM root complex (bus 0); this driver discovers the port over ECAM, runs one RX and one TX buffer-descriptor ring, brings up the MAC + PHY, and exposes the wolfIP poll/send callbacks.
+
+## Model
+
+The board (DDR, clocks, MMU, UART, PCIe/ECAM) is brought up by the boot stage (wolfBoot). This driver runs in the booted application: it enumerates the ENETC port and the shared MDIO controller over ECAM, programs the station-interface (SI) and port registers, sets up the BD rings in memory, and polls them. There is no interrupt path.
+
+It is consumed by the wolfBoot test-app (which links wolfIP core + this driver + the TFTP client). `nxp_enetc.c` is the reusable driver; board parameters live in `nxp_enetc_board.h`.
+
+**Single instance.** All per-device state (base addresses, ring indices, PHY address, BD rings, buffer pools) is held in file-scope `static` variables and `WOLFIP_MAX_INTERFACES` defaults to 1, so the driver drives exactly one MAC. A second port of the same MAC type in one image would share that state; move it behind `ll->priv` first.
+
+## Files
+
+- `nxp_enetc.h` - public API + PCI/ECAM, SI, port, BD-ring and MDIO register map.
+- `nxp_enetc.c` - driver: ECAM config access + BAR setup, MDIO clause-22, PHY detect/reset/autoneg, SGMII PCS / RGMII interface select, BD-ring datapath, wolfIP poll/send callbacks.
+- `nxp_enetc_board.h` - board parameters (ECAM base, port/MDIO function index, PHY address, interface mode). All overridable from CFLAGS.
+- `config.h` - wolfIP compile-time configuration for this port.
+
+## Board parameters
+
+All overridable from CFLAGS. Defaults target the LS1028A-RDB (port 0, external SGMII PHY at MDIO address 0x2 reached through the shared MDIO PF). `nxp_enetc_init()` scans the MDIO bus, so a board with the PHY elsewhere is still detected.
+
+| Define | LS1028A value | Notes |
+|---|---|---|
+| `NXP_ENETC_ECAM_BASE` | `0x01F0000000` | ECAM config space (bus 0) |
+| `NXP_ENETC_IERB_BASE` | `0x01F0800000` | IERB (persistent MAC address) |
+| `NXP_ENETC_PORT_FN` | `0` | ECAM function for the ENETC port (fn0 = port0 SGMII) |
+| `NXP_ENETC_MDIO_FN` | `3` | ECAM function for the shared MDIO controller |
+| `NXP_ENETC_PHY_ADDR` | `0x2` | external PHY on port0 (probed first, then bus scan) |
+| `NXP_ENETC_IF_SGMII` | `1` | `1` = SGMII (configures the internal PCS), `0` = RGMII |
+
+On LS1028A the ENETC ports are: fn0 = port0 (external SGMII PHY on the RDB), fn1 = port1, fn2 = port2 (internal 2.5G to the Felix L2 switch), fn6 = port3, fn3 = the shared MDIO controller. Port0 is the wire-facing path with a real PHY; the internal ports need switch configuration to reach a jack.
+
+## Endianness and cache
+
+ENETC registers and buffer descriptors are little-endian, matching the AArch64 host, so register/BD access needs no byte swap. wolfBoot runs this target with the MMU and D-cache ON and DDR cacheable (required for coherency with the ENETC coherent DMA, SICAR=0x27276767), so the driver does `dc civac` (TX clean) / `dc ivac` (RX invalidate) maintenance around the rings and buffers, plus a `dmb` between BD/buffer stores and the ring doorbell.
+
+## Status
+
+Hardware-verified on the LS1028A-RDB: PHY/link up, DHCP lease, and TCP throughput (~62 MB/s RX, ~30 MB/s TX). The polled `eth_poll`/`eth_send` ring datapath (producer/consumer index, wrap, ring-full and length-clamp bookkeeping) runs on silicon. The bring-up sequence (ECAM discovery, BAR enable, SI/port enable, ring setup, PCS/PHY) follows the U-Boot ENETC driver. Per-PF BAR0 is read live (fallback-assigned only if zero); the MAC address is written via both the SI `PSIPMAR` and the IERB; DMA uses 1:1 addressing (the MMU maps DDR cacheable identity).
+
+`nxp_enetc_init()` populates the `struct wolfIP_ll_dev` (mac/ifname/mtu/poll/send). `eth_poll()`/`eth_send()` move frames through the BD rings with `dmb` ordering and `dc civac`/`dc ivac` cache maintenance.
+
+## Build
+
+The driver is built by its consumer (the wolfBoot test-app) with the AArch64 cross-compiler, e.g.:
+
+```
+aarch64-linux-gnu-gcc -I<wolfip-root> -Isrc/port/nxp_enetc \
+    -c src/port/nxp_enetc/nxp_enetc.c
+```

src/port/nxp_enetc/config.h

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+/* config.h
+ *
+ * wolfIP configuration for the NXP ENETC port (LS1028A / Layerscape).
+ *
+ * Copyright (C) 2026 wolfSSL Inc.
+ *
+ * This file is part of wolfIP TCP/IP stack.
+ *
+ * wolfIP is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfIP is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+#ifndef WOLF_CONFIG_H
+#define WOLF_CONFIG_H
+
+#ifndef CONFIG_IPFILTER
+#define CONFIG_IPFILTER         0
+#endif
+
+#define ETHERNET
+#define LINK_MTU                1536
+
+#define MAX_TCPSOCKETS          4
+#define MAX_UDPSOCKETS          2
+#define MAX_ICMPSOCKETS         1
+#define RXBUF_SIZE              LINK_MTU
+#define TXBUF_SIZE              LINK_MTU
+
+#define MAX_NEIGHBORS           8
+#define WOLFIP_ARP_PENDING_MAX  2
+
+#ifndef WOLFIP_MAX_INTERFACES
+#define WOLFIP_MAX_INTERFACES   1
+#endif
+
+#ifndef WOLFIP_ENABLE_FORWARDING
+#define WOLFIP_ENABLE_FORWARDING 0
+#endif
+
+#ifndef WOLFIP_ENABLE_LOOPBACK
+#define WOLFIP_ENABLE_LOOPBACK  0
+#endif
+
+#ifndef WOLFIP_ENABLE_DHCP
+#define WOLFIP_ENABLE_DHCP      1
+#endif
+
+/* Static IP fallback (used when DHCP is disabled or times out). */
+#define WOLFIP_IP               "192.168.1.10"
+#define WOLFIP_NETMASK          "255.255.255.0"
+#define WOLFIP_GW               "192.168.1.1"
+#define WOLFIP_STATIC_DNS_IP    "8.8.8.8"
+
+#if WOLFIP_ENABLE_DHCP
+#define DHCP
+#endif
+
+#endif /* WOLF_CONFIG_H */