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Pull requests: llvm/circt

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Pull requests list

[AXI4] Add concurrent read/write count to subordinate-like ops
#11062 opened Aug 28, 2026 by TaoBi22 Contributor Loading…
1
[RFC][SV/HW] Split to sv.net and sv.var lvalue types from hw.inout (Phases 1, 2, 3, 5, 6)
#11061 opened Aug 28, 2026 by okekayode Contributor • Draft
4
[FIRRTL][SV] Use localparam to lower constant read probe
#11060 opened Aug 27, 2026 by uenoku Member • Draft
2
[FIRRTL] Preserve constant uses when lowering probes
#11059 opened Aug 27, 2026 by uenoku Member Loading…
1
13
[Moore] Add missing conversions to open array typesAdd support for OpenUnpackedArrayType constants
#11058 opened Aug 27, 2026 by ayush213 Loading…
1
[FIRRTL] Add Registry FIR syntax
#11056 opened Aug 26, 2026 by uenoku Member • 2/2 Loading…
6
[FIRRTL] Warn on abstract resets on extmodule's.
#11055 opened Aug 26, 2026 by dtzSiFive Contributor Loading…
4
[FIRRTL] Add Registry MLIR type
#11054 opened Aug 26, 2026 by uenoku Member • 1/2 Loading…
4
[MLIR] Update SymbolTable::getVisibilityAttrName callers to SymbolOpInterface::getDefaultVisibilityAttrName
#11053 opened Aug 26, 2026 by ethansaurusrex Loading…
1
[AXI4] Add verify-axi4-networks pass
#11052 opened Aug 26, 2026 by TaoBi22 Contributor • 7/7 Loading…
3
[Moore] Support implicit conversion from unpacked array to dynamic array
#11049 opened Aug 25, 2026 by ovdiiuv Loading…
[ImportVerilog] Support enum next, prev, name methods ImportVerilog
#11042 opened Aug 21, 2026 by fabianschuiki Contributor Loading…
5
[datapath] Lower Product of Sum to a Booth Encoded Partial Product Array
#11039 opened Aug 21, 2026 by cowardsa Contributor Loading…
5
[OM] Avoid full module verification in release builds
#11037 opened Aug 20, 2026 by uenoku Member Loading…
6
[ImportVerilog] Fix lvalue conversion for output/inout/ref arguments ImportVerilog
#11033 opened Aug 19, 2026 by fabianschuiki Contributor • 3/3 Loading…
3
[LLHD][Mem2Reg] Finer-grained promotion slots
#11018 opened Aug 18, 2026 by AlviseDeFaveri Contributor Loading…
[HW][Sim] Add SimulationVariableTypeInterface to let hw.inout hold sim value types
#10997 opened Aug 15, 2026 by okekayode Contributor Loading…
3
[Sim] Add sim.assoc_array.clear op Simulator Involving the Sim dialect or other simulation concerns
#10996 opened Aug 15, 2026 by okekayode Contributor Loading…
8
[AXI4] Add xbar op
#10991 opened Aug 14, 2026 by TaoBi22 Contributor • 6/7 Loading…
4
[ImportVerilog] Save the source text of the assert/assume/cover statements.
#10990 opened Aug 14, 2026 by hovhannes-96 Contributor Loading…
1
[BMC] Accept SystemVerilog input
#10983 opened Aug 12, 2026 by 5iri Contributor Loading…
19
[HW] Support struct_inject, struct_explode, and single-field struct_create in HWAggregateToComb
#10981 opened Aug 12, 2026 by jpienaar Member Loading…
10
[FIRRTL] Prototype Registry type and domain insert statement
#10940 opened Aug 4, 2026 by uenoku Member • Draft
6
[FIRRTL][ExportVerilog] add ltl.clocked_atom emission
#10906 opened Jul 26, 2026 by Clo91eaf Contributor Loading…
14
[FIRRTL] Fix stale const types in cat/mux canonicalize
#10905 opened Jul 25, 2026 by AayushMainali-Github Contributor Loading…
3 tasks done
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