LATX, AVX: defer redundant VEX.128 upper-half clears

[luzeng87]

Summary

• defer repeated VEX.128 upper-half clears until the value is observed or the translation block exits
• materialize pending clears before helpers, signals, and context transitions
• exclude mixed XMM/YMM translation blocks from SHBR to preserve full-width liveness
• add instruction-level upper-half and signal-state tests

Validation

• clean 3A6000 x86-64 and i386 builds: passed
• upper-half state tests: passed on native x86, JIT, cold AOT, and hot AOT
• fast test suite: 24 passed, 0 failed

Signed-off-by: Lu Zeng luzeng87@gmail.com

[xiezyang]

该改动会导致部分 YMM 指令的结果未写回目标寄存器，建议修复后再合入。

• VMASKMOVPS/PD 的 YMM 寄存器目标路径只在 XMM 情况下执行 temp -> dest，导致低 128 位保留旧值，高 128 位被错误清零。
  target/i386/latx/translator/tr-avx-mov.c
• VPBLENDVB/W 存在相同问题。
  target/i386/latx/translator/tr-avx.c
  建议无条件将 temp 写回 dest，仅在 XMM 形式调用 set_high128_xreg_to_zero(dest)。

[luzeng87]

Updated with commit 7be22ce to fix the Geekbench 101 hot-AOT crash.

Diagnosis:

• The failing guest TB starts at 0x31a81c5 after DIV and reads YMM10 as four table indices.
• With SHBR enabled, repeated runs of the same hot AOT cache intermittently hit SIGBUS/SIGSEGV because a mixed XMM/YMM TU path corrupted the fourth YMM10 qword.
• Disabling all SHBR made 8/8 runs correct but reduced score from about 760 to about 690.

Fix:

• Skip SHBR only for TBs containing a YMM operand and conservatively keep all vector registers live.
• Pure XMM/SSE TBs still use SHBR.

Validation on 3A6000 @ 2.5 GHz:

• Before: repeated hot-AOT runs failed intermittently with rc=135/139.
• Full SHBR disabled: 8/8 pass, scores 686-690.
• Selective fix: cold 670; hot AOT 10/10 pass, scores 758-762.
• Extended AVX integration fixture: native, JIT, cold AOT, and 10 hot-AOT runs pass.

[luzeng87]

Correctness recheck found reproducible YMM failures on this head. Repairing the three missing temporary-to-destination writes is not sufficient: the mixed XMM/YMM state regression still fails in a clean LoongArch build. This broad deferred-state change is not safe to merge; closing it rather than adding more fixes to the stack.

[luzeng87]

Added commit 3dabdd4 to restore full-width destination writeback for YMM VMASKMOVPS/VMASKMOVPD, VPBLENDVB, and VPBLENDW. The earlier deferred-zeroing change incorrectly made the destination copy conditional on an XMM destination and then applied upper-half clearing to YMM destinations.

Validation on LoongArch 3A6000:

• focused register-result test: JIT, cold AOT, and hot AOT all exit 0
• non-empty hot AOT artifact: 4,432 bytes
• meson test --suite lat-pr-fast --print-errorlogs: 24/24 passed
• tested latx-x86_64 SHA-256: 9b183be06cf20a7f20d1cc6b4d8f7c017def6ea09656d5f2f40a9ae90f94116b

The PR remains a draft while the wider AVX deferred-zeroing cases are reviewed.