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These 2 compiler directives are defined in Annex E of the 1800-2017
I ran into this while attempting to parse some stdcell libraries.
I unfortunately can't seem to add all of the annex directives as the nom crate seems to have an issue
digging deeper when attempting to use the alt function in sv-parser-parser/src/general/compiler_directives.rs:L9
the nom alt function supports only up to 21 elements, placing all of them breaks this.
regardless, without these two directives I can't parse said Verilog.
Yup, cascading alts worked 🥳
I added back delay_mode_unit and delay_mode_zero
I will mention this commit misses support for default_trireg_strength and default_decay_time as they might need a new literal? (default decay time valid values are either integerconst, realconst or the word infinite)
I've done some more testing and It seems I've implemented something slightly wrong here, when I have a file with one of these directives defined and a module defined afterwards it seems to break the syntax tree.
maor1993
changed the title
preparser: adding 2 optional compiler directives delay_mode_path , delay_mode_distributed
WIP:preparser: adding 2 optional compiler directives delay_mode_path , delay_mode_distributed
Feb 27, 2025
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These 2 compiler directives are defined in Annex E of the 1800-2017
I ran into this while attempting to parse some stdcell libraries.
I unfortunately can't seem to add all of the annex directives as the
nomcrate seems to have an issuedigging deeper when attempting to use the alt function in
sv-parser-parser/src/general/compiler_directives.rs:L9the nom alt function supports only up to 21 elements, placing all of them breaks this.
regardless, without these two directives I can't parse said Verilog.