systems & hardware · IIIT Bangalore
C++ FPGA HLS SystemVerilog Computer Architecture
systems & hardware · IIIT Bangalore
C++ FPGA HLS SystemVerilog Computer Architecture
This project implements the Radix-2 Fast Fourier Transform (FFT) algorithm on an FPGA using Xilinx DSP48 IP blocks. The design leverages the parallel processing capabilities of FPGAs to achieve hig…
Forked from TeoZakeru/Accident-Detection-and-Alert-System
The 'Accident Detection and Alert System' code for an Arduino platform is available in this repository. Using sensors, the system is intended to identify accidents and notify pre-identified emergen…
C++ 1
Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.
This is the ELCIA (2024) hackathon entry by Team SLL to develop a refreshable braille display.
Python 1
Forked from anirudh-pathaneni/HealthCare-with-Alerts-Summarizer
Python