Ability to import specific module from Verilog/model from BLIF without making its io the block's IO - #398

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mdko wants to merge 11 commits into

UCSBarchlab:developmentfrom

pllab:submodule-import

Commits on Jul 9, 2021

Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
mdko
committed
fccb1d5

Commits on Jul 23, 2021

improve rom verilog output
vegaluisjose
committed
e3cbf0c

Commits on Aug 4, 2021

Merge pull request #399 from vegaluisjose/improve_rom
mdko
authored
40f1863
Improve Verilog output when a memory doesn't have any writes
mdko
committed
0413976
Merge pull request #400 from pllab/verilog-output-update
mdko
authored
2d9ab35
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
mdko
committed
298fb4b
Merge branch 'submodule-import' of https://github.com/pllab/PyRTL into submodule-import
mdko
committed
a6317ca
Don't generate nands on BLIF import
mdko
committed
750cc70
Merge pull request #401 from pllab/blif-import-update
mdko
authored
e15cf0d
Ability to import specific module from Verilog/model from BLIF without making its io the block's IO
mdko
committed
5d628c6
Merge branch 'submodule-import' of https://github.com/pllab/PyRTL into submodule-import
mdko
committed
6461ae9