name: "Abhinav Venkata K"
role: "ECE Enthusiast | Systems Thinker | Hardware-Software Co-Designer"
degree: "B.Tech, Electronics & Communication Engineering"
focus:
- Computer Architecture & RISC-V
- Compiler Engineering (LLVM / MLIR)
- VLSI Design & RTL Verification
- Systems-Level Software Development
philosophy: "Engineering systems from transistor-level to compiler-level — where silicon meets software."I'm an Electronics & Communication Engineering student with a systems-level mindset spanning VLSI design, compiler engineering, and computer architecture. I enjoy building at every layer of the compute stack — from RTL and transistor-level circuits to LLVM-backed compilers.
I approach engineering with first-principles thinking, rigorous validation, and a curiosity for how hardware and software co-design shapes performance, power, and reliability.
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Stack
RISC-V Processor — Custom Processor in Verilog
A custom RISC-V processor implementation built from scratch in Verilog. Multi-stage pipeline architecture supporting core RISC-V integer instructions with full testbench infrastructure for functional verification.
| Attribute | Details |
|---|---|
| Stack | Verilog, RISC-V ISA, Digital Design |
| Scale | Multi-module pipelined architecture |
| Performance | Cycle-accurate RTL simulation |
| Impact | Open-source RISC-V learning platform |
| Repository | DevAbhinav-23/RISC-V-Processor |
Demonstrates understanding of computer architecture fundamentals from datapath design to control logic synthesis, including hazard detection and forwarding.
TinyC Compiler — LLVM-Powered Compiler from Scratch
A complete compiler for the TinyC language built using LLVM, Flex, and Bison. Supports functions, variables, arithmetic, control flow (if/else, while, for), and print statements.
| Attribute | Details |
|---|---|
| Stack | C++, LLVM, Flex, Bison, CMake |
| Scale | Full compiler pipeline: lexer to native codegen |
| Performance | LLVM-optimized machine code output |
| Impact | Educational compiler framework |
| Repository | DevAbhinav-23/TinyC_Compiler |
Frontend handles lexing and parsing into an AST, while LLVM manages IR generation and native code optimization. Includes comprehensive test suite.
TinyC Compiler (MLIR) — Dual-Backend with LLVM and MLIR
An evolution of the TinyC compiler featuring a dual-backend architecture powered by both LLVM and MLIR. Implements custom MLIR dialects for progressive IR lowering.
| Attribute | Details |
|---|---|
| Stack | C++, LLVM, MLIR, Custom Dialects |
| Scale | Multi-backend IR transformation pipeline |
| Performance | MLIR-based progressive lowering |
| Impact | Next-gen compiler architecture research |
| Repository | DevAbhinav-23/TinyC-Compiler |
Explores the frontier of domain-specific compiler optimization using MLIR's extensible framework for hardware-aware code generation.
C-Shell — Collaborative Shell-Based Document Management
A C-based shell implementation with lexer, parser, builtins, and executor modules. Designed as a collaborative document management platform combining shell scripting with structured file operations.
| Attribute | Details |
|---|---|
| Stack | C, Shell Scripting, Unix IPC |
| Scale | Full-featured document management system |
| Performance | Low-overhead process management |
| Impact | Open-source collaborative CLI tool |
| Repository | DevAbhinav-23/C-Shell |
Modular architecture separating concerns across lexical analysis, parsing, command execution, and builtin management.
4-Stage Audio Amplifier — Analog Circuit Design
Complete 4-stage audio amplifier design featuring differential pre-amplifier, common-emitter gain stage, active band-pass filter, and Class-AB power output stage.
| Attribute | Details |
|---|---|
| Stack | Analog Electronics, Circuit Design, TeX |
| Scale | 4-stage amplifier chain |
| Performance | Multi-stage gain optimization |
| Impact | Hands-on analog design proficiency |
| Repository | DevAbhinav-23/4-Stage-Audio-Amplifier |
Covers full analog design flow from small-signal analysis through large-signal power stage design with frequency response characterization.
SP Lab Project — Sampling Reconstruction & Instrument Clustering
Signal processing project implementing non-ideal sampling reconstruction and automated drum hit detection with instrument clustering using ML.
| Attribute | Details |
|---|---|
| Stack | MATLAB, DSP, Machine Learning |
| Scale | Multi-stage signal processing pipeline |
| Performance | Real-time drum hit detection |
| Impact | Applied DSP research project |
| Repository | DevAbhinav-23/SP-Lab-Project |
Combines classical DSP techniques with ML-based audio classification for real-world signal analysis.
5-Bit CLA Adder — VLSI Carry Lookahead Adder
A 5-bit Carry Lookahead Adder implemented in Verilog demonstrating parallel prefix computation, carry generate/propagate logic, and area-delay-power trade-offs.
| Attribute | Details |
|---|---|
| Stack | Verilog, VLSI Design, Digital Logic |
| Scale | 5-bit parallel prefix adder |
| Performance | O(log n) carry propagation |
| Impact | High-speed arithmetic circuit design |
| Repository | DevAbhinav-23/5-Bit-CLA-Adder |
Demonstrates understanding of parallel prefix computation and the trade-offs between area, delay, and power in high-performance arithmetic circuits.
LMS Adaptive Filter — Adaptive Signal Processing
An LMS adaptive filter implementation for real-time filter coefficient adaptation in system identification and noise cancellation applications.
| Attribute | Details |
|---|---|
| Stack | MATLAB, Adaptive Algorithms, DSP |
| Scale | Real-time adaptive filter |
| Performance | Convergence-optimized LMS |
| Impact | Applied adaptive signal processing |
| Repository | DevAbhinav-23/LMS-Adaptive-Filter |
Practical DSP algorithm design with convergence analysis for noise cancellation applications.
learning:
- RISC-V ISA Extensions & Custom Accelerators
- MLIR Dialect Design for Hardware Abstractions
- Advanced VLSI Physical Design
building:
- Custom RISC-V Processor with ISA Extensions
- LLVM/MLIR Compiler Infrastructure
exploring:
- Chiplet Architecture & Modular SoC Design
- Rust for Systems-Level Tooling
open_to:
- VLSI Design & Verification Internships
- Compiler Engineering Roles
- Embedded Systems Development
"Engineering systems from transistor-level to compiler-level — where silicon meets software."